Electromigration (EM) is the motion of ions through a conductor in response to the passage of current through the conductor. A divergence of ionic flux under the force of an "electron wind" may lead to the creation of vacancies, thus forming voids or holes in the conductor. The growth of the voids within a conductor may eventually lead to an open-circuit failure of the conductor. Accordingly, electromigration is a serious and destructive wear out phenomenon.
Electromigration within the power supply circuitry (also termed the "power net") of an integrated circuit (IC) has serious consequences for the reliability of the IC, and also serves to reduce substantially the product life of the IC. The metal lines, vias, substrate taps and contacts which comprise the power net of an IC must all comply with predetermined electromigration design specifications to ensure the reliability of the IC. More specifically, the direct current flow through each fragment of the power net must be established, and compared to a predetermined maximum direct current threshold for the power net fragment in a process known as electromigration analysis.
The direct current flow through each power net fragment is established by performing a simulation of the operation of the power net and determining the anticipated voltage and current characteristics of the power net. Such simulations of the operation of the power net of an IC are often conducted on a resistor network "extracted" or derived from the symbolic layout of an IC. Resistor networks are typically extended from the symbolic layout of an IC soley for the purpose of simulating the electrical characteristics of the IC. Symbolic layouts provide a convenient and readily available representation of the IC from which to extract a resistor network.
Symbolic layout techniques allow an IC designer to produce a low-level representation of the layout of an IC, while alleviating some of the burden associated with polygon layout techniques. More specifically, when creating a polygon layout (also commonly termed the "mask layout" or "mask pattern") of an IC in the first instance, a designer is required to locate every conductor via and contact of every component. Accordingly, the design of a simple transistor can require the designer to locate a number of transistor components. Furthermore, an IC designer creating a polygon layout must have a thorough understanding of the geometric design rules associated with polygon layout techniques.
Symbolic layout techniques provide a higher degree of design abstraction and automation and allow the IC designer to access a library of pre-defined symbols for regularly repeated components or cells. For example, a predetermined transistor structure could be symbolically defined, thus allowing the designer to repeat the transistor structure in a representation of an IC fragment in the so-called "symbolic domain". This representation is then termed the symbolic layout of the IC fragment. A number of design tools for producing symbolic layouts are commercially available, such as the Virtuoso.RTM. IC layout package developed by Cadence Design Systems, Inc., of San Jose, Calif. The symbolic layout may then be used automatically to generate a polygon (or mask) layout for the IC. For example, the Virtuoso.RTM. layout package includes a "compactor" for converting and compacting symbolic layouts into polygon layouts.
Once a resistor network has been extracted from the symbolic layout, the process enters a network reduction phase, wherein the resistor network is "reduced" according to well-known reduction techniques. Specifically, the resistors which comprise the resistor network may be combined in various ways to reduce the size and complexity of the resistor network. The electrical performance of the extracted portion of the IC, represented by the "reduced" resistor network, can then be simulated on a number of simulation software packages, such as SPICE, Spectre.RTM. or TimeMill.RTM., to perform the electromigration analysis.
A number of problems are associated with extracting a resistor network from a symbolic layout. The symbolic layout must be "clean" before the resistor network can be properly extracted. A "clean" symbolic layout is one in which all cells or components are properly connected and not overlayed on each other, and information regarding current flow in the IC is correctly represented. The process of generating a "clean" symbolic layout for the purposes of resistor network extraction is a time-consuming and labor intensive exercise.
It is also known to extract resistance information from a polygon layout representation of an IC. One such disclosure is given by M. Horowitz and R. W. Dutton, "Resistance Extraction from Mask Layout Data," IEEE Transactions on CAD, Vol. CAD-2, No. 3, July 1983, pp. 145-150. The document discloses fracturing a complex polygon into a number of smaller pieces or fragments for resistance extraction. Specifically, the algorithm requires the determination of current flow within the polygon, and proposes fracturing the polygon along lines perpendicular to the current flow. This algorithm, however, results in a collection of polygon fragments having irregular and complex shapes. The calculation of resistance values for these polygons of irregular shape may be difficult and is not suited for fast resistor network reduction during the network reduction phase discussed above.
In the article by H. Yoshimura, K. Tansho, N. Ohwada, and T. Nishide, "An Algorithm for Resistance Calculation from IC Mask Pattern Information," Proc. Int. Symp. Circuits and Systems, pp. 478-481, 1979, there is disclosed a method of dividing polygons into rectangles by drawing vertical and horizontal lines from all vertexes of a polygon. However, this division is performed merely to determine current direction and not for the purposes of extracting a resistor network from the polygon.
As the number of active components implemented within an IC grows, the determination of the electrical characteristics, and particularly the electromigration analysis process, is becoming increasingly taxing on simulation software. Known techniques of electromigration analysis can require a number of days to complete as a result of the time required for the fracturing of polygons, the calculation of resistance values for complex polygon fragments, and the simulation of a resistor network comprising millions of resistors. Therefore, a need exists for a method which balances the speed and accuracy requirements of the electromigration analysis process.